This invention relates in general to substrate coating techniques and in particular to a new and useful process for coating a substrate surface which has cavities thereon of relatively small size.
Metallization in microelectronics, among other things, has to fulfill the task of ensuring electrical contact between the plane of the strip conductors and the components which lie outside of this plane and are separated from it by an insulating layer. For this purpose, the strip conductors must have the lowest possible electrical resistance, even over steep steps. This presupposes good step coverages (ratio between the layer thickness at the side of a cavity to the layer thickness in the plane of the conductor strips).
It was possible to solve the problem of step coverage by suitably orienting the substrate to be coated with respect to the coating source, by an elevated temperature and by the appropriate choice of the side angle (Ref. 1). Arrangements are known (Ref. 2), in which vaporizing sources were combined with substrates mounted on planetary gears. A further possibility consists of flattening or levelling steps by vapor-coating them with a dielectric layer before they are metallized. This process was described, above all, for SiO.sub.2 layers (Ref. 2, Ref. 3). Attempts have also been made to utilize wide vapor sources, so that the vapor molecules, as far as possible, strike the substrate from all directions, in order to coat surfaces of all inclinations as uniformly as possible in this manner. A similar effect is also achieved as a result of gas scattering when the coating process is carried out at a relative high pressure (more than 0.5 Pa), for example, with so-called magnetron sources (Ref. 4).
All known processes, however, have the disadvantage that they are suitable enough for achieving a better step coverage, as long as the cavity is wide in relation to its depth, but that they fail, when the ratio of depth to width (named "aspect ratio") is about 1 or higher. Such step ratios are, however, constantly becoming more important in microelectronics for the so-called VLSI (Very Large Scale Integration) technique, which is playing a constantly more significant role in recent times.
Admittedly, by combining sputter deposition with a simultaneous sputter etching (bias sputtering), it has been possible to practically level trenches with a ratio of 1:1 with aluminum. However, when coating cavities, trenches or holes with an aspect ratio of more than one (not as wide as they are deep), difficulties do arise than with bias sputtering. Because sputter source always is an extended source, the particles strike the substrate surface, which is to be coated, at different angles. As a result, the individual edges of steps, which are far apart, are admittedly, coated well all-around, as described. For the narrow cavities considered here, however, this process of coating from all directions is disadvantageous. Thorough investigations have namely revealed that the layer grows more readily at the edges than in the remaining places of the cavities. As a result, overhangs are formed at the edges. These overhangs gradually narrow the openings of the cavities, until caves are finally formed. Such caves are undesirable, because they readily give rise to defects in the microcircuits.